There are many kinds of flash EEPROM cells, and one example of them is illustrated in FIG. 3.
FIG. 3A illustrates a conventional EEPROM cell having a simple stacked type gate structure. As shown in this drawing, a control gate 31 and a floating gate 32 are formed by utilizing two layers of polysilicon, and source and drain regions 33 are formed on the opposite sides of the floating gate. A channel region is formed between the source and drain regions, and is covered by the floating gate. The EEPROM cell of such type is disclosed in U.S. Pat. Nos. 3,984,822 and 4,698,787.
FIG. 3B illustrates another conventional EEPROM cell in which a split gate structure is provided. In this EEPROM cell, a control gate 34 and a floating gate 35 are formed by utilizing two layers of polysilicon, like the simple stacked gate structure. However, a difference is seen in that the floating gate 35 covers only a part of the channel region, and that source and drain regions 36 are formed on a side of the control gate and on a substrate. The EEPROM cell of this type is disclosed in U.S. Pat. No. 4,998,220.
FIG. 3C illustrates still another conventional EEPROM cell having three layers of polysilicon, thereby including an erasing gate. That is, three polysilicon layers form a control gate 37, a floating gate 38 and an erasing gate 39. The erasing gate 39 which is formed by a third polysilicon layer is provided on an isolated region which is a field oxide layer 40 formed on a split type cell structure (this is disclosed in U.S. Pat. No. 5,070,032, in particular FIG. 2B thereof). Another type is constituted as follows. An erasing gate is formed between a floating gate and a field oxide layer by utilizing a first polysilicon layer, and the floating gate and a control gate are formed from the second and third polysilicon layers (this is described in International Electron Devices Meeting (IDEM) Technical Digest, Dec. 1984, pages 464-467).
Programming such an EEPROM and erasing a programmed data from the EEPROM are carried out in the following manner.
First, a programming operation, i.e., recording data into the EEPROM having the simple stacked type gate as in FIG. 3A, is carried out in the following manner. That is, a positive voltage, which is significantly higher than the usual voltage, is supplied to the control gate and drain. Thus, hot electrons are formed in the channel near the drain. Some hot electrons are injected into the floating gate by the positive voltage induced in the floating gate, thereby the programming is carried out.
Meanwhile, an erasing operation is carried out in the following manner. A positive voltage is supplied to the source, and the control gate is grounded. Then owing to the electric field between the floating gate and the source, the electrons which have been injected into the floating gate are tunneled through a thin tunneling oxide film toward the source, with the result that the recorded data are erased.
The operation of recording or erasing a data to and from the EEPROM cell which has floating gate and control gate which are disposed unevenly over the channel, as in FIG. 3B and unlike the simple stacked gate type, will be described. A programming operation is carried in the same manner as that of the simple stacked gate type EEPROM. An erasing is carried out by supplying a positive voltage to the drain instead of the source, so that an erasing would be done through an F-N tunneling between the floating gate and the drain.
Of these conventional techniques, the simple stacked gate type EEPROM as in FIG. 3A has the following problems: over-erasing occurring during an erasing operation; source junction breakdown due to a high voltage supplied to the source during an erasing operation; and quality deterioration of the gate oxide layer.
In the EEPROM in which the floating gate and the control gate are disposed unevenly with the channel as in FIG. 3B, there is a drain junction breakdown problem, and quality deterioration of the gate oxide layer.
In the structure as in FIG. 3C having the erasing gate, erasing is carried out through an F-N tunneling between the floating gate and the erasing gate, and therefore, the above mentioned problems are not seen. However, there are the following problems: three, rather than two, layers are required; the process of forming the poly structure with three layers is complicated; and the topology is aggravated.